Corollary Theorems: Flip Flops

 

ELECTRONIC DESIGN NOTES #12

Flip-Flops
 
 

 
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The topic of Logic Gates is structured in this page according to the following:
1. NAND Gates Flip-Flops
2. NOR Gates Flip-Flops
3. SR Flip-Flops
4. J-K Flip-Flops
5. D Flip-Flops
6. T Flip-Flops

NOTE
The basic notions highlighted in this page are related to electronic design topics presented in the first part Hardware Design of Learn Hardware Firmware and Software Design.
  
NAND GATES FLIP-FLOPS

The problem with Flip-Flops is, you cannot let them have any state. In order to start a NAND Flip-Flop you need to set HIGH both the SET and the RESET pins. The principle is better exemplified if you replace the NAND Gates with their equivalents--OR Gates having negated inputs.

The outputs are Q and Q and they complement each other.
 


NAND FLIP-FLOP
 
Schematic Timing Diagram Truth Table Description
Flip-Flop NAND Flip-Flop timing NAND
SET RESET Q Q
1 1 0 1
0 1 1 0
1 0 0 1
0 0 0 1
Fig 1: NAND Gates Flip-Flop

 
NOR GATES FLIP-FLOPS

The NOR gate Flip-Flop is more "user friendly", meaning, you can start it with both SET and RESET pins being LOW.

 


NOR FLIP-FLOP
 
Schematic Timing Diagram Truth Table Description
Flip-Flop NOR Flip-Flop timing NOR
SET RESET Q Q
0 0 0 1
1 0 1 0
0 1 0 1
0 0 1 0
Fig 2: NOR gates Flip-Flop

SR FLIP-FLOPS

The SR Flip-Flop works similar to the NOR Gate Flip-Flop, but it is more complex. First, let's take a look at a SR Flip-Flop truth table.

 


SR FLIP-FLOP
 
Schematic Timing Diagram Truth Table Description
Flip-Flop SR Flip-Flop timing SR
# SET RESET Q Q Allowed
1 0 0 0 1 yes
2 0 0 1 0 yes
3 0 1 0 1 yes
4 0 1 1 0

unstable
5 1 0 0 1 yes
6 1 0 1 0 yes
7 1 1 0 0 no
8 1 1 0 0 no
Fig 3: SR Flip-Flop


Please note positions #7 and #8 in the truth table: both of them are forbidden because the outputs do not complement each other. In addition position 8 is unstable and Q will change its state from 0 to 1 and back continuously.

State #4 it is also unstable; in this case Q may be 0, although it shouldn't--in the Truth Table Q is marked as 1.

The point to note is, SR Flip-Flops require a certain sequence of operation, and they need to be protected against accidental situations as are #4, #7, and #8.
J-K FLIP-FLOPS


J-K Flip-Flop has few advantages over the SR one. There are no forbidden or indeterminate states, and it complements well. In addition, the J-K Flip-Flops are used in Master-Slave constructions--this topic is explained further in this page.

 


J-K FLIP-FLOP
 
Schematic Timing Diagram Truth Table Description
Flip-Flop J-K Flip-Flop timing J-K
# SET RESET Q Q Allowed
1 0 0 0 1 yes
2 0 0 1 0 yes
3 0 1 0 1 yes
4 0 1 1 0

yes
5 1 0 0 1 yes
6 1 0 1 0 yes
7 1 1 0 1 yes
8 1 1 1 0 yes
Fig 4: J-K Flip-Flop

The outputs change their state when:
1. the input conditions are met
2. on the next falling edge of the clock

 
D FLIP-FLOPS

Undeniably, the D Flip-Flop it is the easiest one to work with. The name D comes from Data. This Flip-Flop is perfectly stable, and very easy to control. Fact is, the D Flip-Flop is the best!


D FLIP-FLOP
 
Schematic Timing Diagram Truth Table Description
Flip-Flop D Flip-Flop timing D
D Q Q
0 0 1
1 1 0
Fig 5: D Flip-Flop
Q takes the value of D on the next falling clock edge

 
T FLIP-FLOPS

Some applications require that we change Q on each input toggle, without any clock, therefore we can use T Flip-Flops for that. However, there are T Flip-Flops built with a clock, and in that case the T Flip-Flop behaves exactly like the D one. Particular to the T Flip-Flop is, it triggers the outputs only when T changes states from 0 to 1.

 


T FLIP-FLOP
 
Schematic Timing Diagram Truth Table Description
Flip-Flop T Flip-Flop timing T
T Q Q
0 0 1
1 1 0
Fig 6: T Flip-Flop
Q takes the value of T


 

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